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bodog888功放
新颖的电源调制比提升的D类AMPS提供更高的效率。/1.8V静态电流1.8V电源
低静态电/双轨G类操作
bodog888功放
  • bodog888功放系列零件

    ·最小立体声放大器IC和下BOM ·最低BOM集成电阻器I2C增益控制

  • 应用场景

    AB类放大器结构/在125MW的整个功率范围内具有优良的THD 优秀的THD在3.6W+3.6W立体声输出功率范围内/30MW时THD<100dB

文档下载
  • Au53xx_GUI_Errata_V1.27.5
    2020-02-04
    .zip
  • Au531x GUI V1.27.5
    2019-12-07
    .zip
  • Au531x GUI V1.26
    2019-09-09
    .zip
  • Au531x GUI V1.25
    2019-07-24
    .zip
  • Au531x GUI V1.24
    2019-07-24
    .zip
  • Au531x GUI V1.23
    2019-07-24
    .zip
  • Au531x GUI V1.22.5
    2019-05-10
    .zip
  • Au531x GUI V1.23.1
    2019-05-10
    .zip
  • Au531x OTF C code V1.4
    2019-03-09
    .zip
  • Au531x OTF C code V1.2
    2019-02-25
    .zip
  • Au531x OTF C code V1.1
    2019-02-25
    .zip
  • Au531x OTF C code V1.0
    2019-02-25
    .zip
  • Au531x OTF C code V0.2
    2019-02-25
    .zip
  • Au531x OTF C code V0.1
    2019-02-25
    .zip
  • Au531x GUI V1.19.2
    2019-02-25
    .zip
  • Au531x GUI V1.20
    2019-02-25
    .zip
  • Au531x GUI V1.18
    2019-02-25
    .zip
  • Au531x GUI V1.17.2
    2019-02-25
    .zip
  • Au531x GUI V1.16
    2019-02-25
    .zip
  • Au531x GUI V1.15
    2019-02-25
    .zip
  • Au531x GUI V1.08
    2019-02-25
    .zip
  • Au531x GUI V1.07
    2019-02-25
    .zip
产品介绍

General Description
The Au53x5/x4/x2 is a Programmable Quad Fractional Frequency translation based jitter attenuating clock synthesizer family of parts with flexible input to output frequency translation options. It supports up to 4 input clocks that are common for all the 4 fractional translations and provides 10 (Au5315/25) or 4 (Au5314/24) or 2 (Au5312 /22) clock outputs. The clock outputs can be derived from the 4 PLLs in a highly flexible manner. It is fully programmable with the I2C / SPI interface or an on chip two time programmable non-volatile memory for factory pre-programmed devices. Using advanced design technology, it provides excellent integrated jitter performance as well as low frequency offset noise performance while working reliably for ambient temperatures from -40 C to 85 C. The chip has best in class transient performance features in terms of clock switching transients and repeatable input to output delays.

Nomenclature:
Au5315/25: 4 input, 10 output, 64-QFN 9mm X 9mm
Au5314/24: 4 input, 4 output, 44-QFN 7mm X 7mm
Au5312/22: 4 input, 2 output, 44-QFN 7mm X 7mm Au531x (Au5315/14/12): VDDIN= VDD= 3.3V/2.5V Au532x (Au5325/24/22): VDDIN= 3.3V, VDD= 1.8V

Features
● Flexible quad PLL frequency translation from a common input: 4 fractional output domains from single input
● Fully Integrated Fractional N PLLs with integrated VCO and programmable loop filter (1 mHz to 4 kHz)
● Wide frequency support
- Differential Output from 8 KHz to 2.1 GHz
- Single Ended Output from 8 KHz to 250 MHz
- Support for 1 Hz frequency on one output
- Differential Input from 8 KHz to 2.1 GHz
- Single Ended Input from 8 KHz to 250 MHz
- Multiple Crystals / XO / TCXO / OCXO support
● LVPECL, CML, HCSL, LVDS and LVCMOS Outputs
● 125 fs typical rms integrated jitter performance
● Synchronized, holdover or free run operation modes
● Hitless input clock switching: Auto or manual
- Sub 50ps phase build out mode transients
- Phase Propagation with programmable slopes
- Frequency ramp for plesiochronous clocks with programmable slopes
- Robust and fast cycle slip and frequency step detection for input frequency steps (Clean frequency tracking for large frequency steps)
● Excellent Close-in Phase noise performance with no external discrete VCXOs or passive external filters
● Digitally Controlled Oscillator mode: to 0.005 ppb
● Programmable Output Delay Control
● Programmable Frequency Ramp Slopes for Switching Pleisochronous Clocks
● Indicators: Lock Loss, Clock Loss, Frequency Drift
● Repeatable Input to Output delays for each power up of chip
- Zero Delay Buffer mode also possible on any one PLL
- Output wake up sync with an independent clock also possible